An automated pipeline transforming natural-language ideas into circuit schematics through LLM-guided C code generation, recursive compilation, and hardware synthesis.
From natural language to hardware in six composable, independently replaceable stages.
LLM synthesizes C code from natural-language idea with hardware-oriented characteristics.
gcc compilation with error classification and LLM-driven correction loop (up to 5 iterations).
License metadata insertion for circuit IP provenance tracking.
20 static heuristic tests per source line across 5 categories (UX, regression, unit, blackbox, A-B).
10 software design patterns checked including singleton, observer, modularity, and memory safety.
Flux API circuit synthesis with graceful degradation to mock JSON generation.
Evaluated on 15 benchmark ideas across 5 hardware target architectures.
| Target | Success Rate | Mean Iterations | Mean LOC |
|---|---|---|---|
| ASIC | 80% | 3.2 | 47.8 |
| FPGA | 93% | 2.4 | 52.3 |
| TPU | 67% | 4.1 | 38.5 |
| QPU | 60% | 4.7 | 29.2 |
| OPU | 75% | 3.5 | 35.6 |
| Overall | 75% | 3.6 | 40.7 |
Key design decisions and their rationale.
C is the most represented systems language in LLM training data. Mature HLS toolchain (Vivado, Intel HLS) provides a proven compilation path to hardware.
Single-pass compilation achieves 31% success rate. Our recursive loop with R=5 achieves 75% — a 2.4× improvement.
Generated code targets hardware unavailable at test time. Static heuristic tests provide coverage without requiring hardware availability.
zsh wrapper for developer familiarity and composability. TypeScript backend for type safety across the six-stage pipeline.
From Natural Language to Hardware: The Idea2Circuit Pipeline for Automated Circuit Synthesis via LLM-Guided Code Generation and Iterative Compilation
We present Idea2Circuit, an automated pipeline that transforms natural-language descriptions of computational ideas into hardware circuit schematics targeting ASIC, FPGA, TPU, QPU, OPU, LPU, and GPU architectures. The system employs a multi-stage architecture comprising LLM-based C code generation, recursive validation and error-corrected compilation using gcc, static heuristic test generation at 20 tests per source line, design pattern conformance checking, and hardware synthesis via the Flux compilation API. The pipeline achieves correct-by-construction C code within a mean of 2.4 validation iterations on a corpus of 15 benchmark ideas, with a 93% success rate for FPGA-targeted circuits.
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